Cirrus Logic EP93xx - Manual (Page 706)

22-18 DS785UM1
Copyright 2007 Cirrus Logic
AC’97 Controller
EP93xx User’s Guide
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AC97RGIS
Address:
0x8088_008C - Read Only
Definition:
Raw Global Interrupt Status Register. The AC’97 raw global interrupt status
register is a read/write register that gives the status of various functions
outside of the FIFO functionality within the controller.
Bit Descriptions:
RSVD: Reserved. Unknown During Read.
SLOT2TXCOMPLETE:Set when the AC97S2Data register has completed
transmission. This bit is cleared when data is in the
register to be transmitted.
CODECREADY: This bit is set to “1” during a wakeup when the codec
indicates that it is ready by setting bit 15 of Slot0. It is
cleared by writing to Bit1 of the AC97EOI Register.
WINT: RAW Wake-up Interrupt Status. If this bit is set to “1”. The
RAW Wake-up interrupt is asserted. This bit is cleared
with a write to the AC97EOI register.
GPIOINT: The GPIOINT shows the raw status of the GPIOINT bit
(slot 12 bit 0) in the receive frame, which is stored in
the AC97S12Data register. This bit is cleared when
the AC97S12Data register is read.
GPIOTXCOMPLETE:GPIO Transmission Complete. Set when a new value to
the AC97S12Data register has completed
transmission. Cleared when data is placed in the
register to be transmitted.
SLOT2RXVALID: The AC97S2Data register has new data that has not been
read. Reading the data in the AC97S2Data register
clears this bit.
SLOT1TXCOMPLETE:Set when the AC97S1Data register has completed
transmission. This bit is cleared when data is written
to the AC97S1Data register to be transmitted.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD SLOT2TX
COMPLETE
CODEC
READY
WINT GPIO
INT
GPIOTX
COMPLETE
SLOT2RX
VALID
SLOT1TX
COMPLETE