3 steps for clock configuration, 6 power management, 1 clock gatings – Cirrus Logic EP93xx User Manual
Page 135: 3 steps for clock configuration -9, 6 power management -9, 1 clock gatings -9
DS785UM1
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Copyright 2007 Cirrus Logic
System Controller
EP93xx User’s Guide
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5.1.5.3 Steps for Clock Configuration
The boot ROM must contain code that performs the following steps for a 14.7456 MHz
crystal. The actual register values should be taken from the register descriptions for the
desired clock setup.
1. After power up, the reset state of all clock control registers (all bits zero) will ensure that
FCLK and HCLK are running at the crystal oscillator frequency of 14.7456 MHz.
2. Configure PLL1 to multiply by the desired value, set HCLK and FCLK rates, and power it
up. To do this: write the proper value (taken from the register table) to
immediately followed by 5 NOP instructions to flush the ARM Core’s instruction pipeline.
The ARM Core will go into Standby mode while PLL1 stabilizes, then it returns to normal
operation at the new clock rates.
3. Configure PLL2 to multiply by the desired value. To do this, write the proper value to
4. Wait for PLL2 to stabilize (at least 1 ms)
5. Program all other clock dividers to the desired values and enable them. The clocks won’t
actually begin running until the clock sources which feed them are enabled. Write the
desired values to these registers:
•
•
•
•
6. All peripherals are now running from divided PLL outputs. Once the clocks have been
configured, the frequency of any peripheral clock can be changed on-the-fly. To do this,
perform a write to the clock register with the new divisor value and then set the
appropriate enable bit. This ensures a problem-free change of the clock.
5.1.6 Power Management
The device follows a power-saving design plan. Power management is done by either
altering the PLLs or the clock system frequency or by shutting off clocks to unused blocks.
Also, there are several system power states to which the device can transition in order to
save power. Care must be taken to ensure the clock system is not put into a non-operational
state and that clock system dependencies are observed.
5.1.6.1 Clock Gatings
The list of peripherals with PCLK gating is shown
. Refer to the appropriate chapter
in this user’s guide to find detailed information about clock gatings for a specific peripheral.