Cirrus Logic EP93xx - Manual (Page 308)

9-6 DS785UM1
Copyright 2007 Cirrus Logic
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
9
9
9
Complete state. Thus, the Carrier Deference state may be entered and exited immediately, or
there may be a delay depending on the state when entered.
Figure 9-4. Carrier Deference State Diagram
When CRS becomes active, the Line Busy state is entered. This state is held until CRS
returns to clear which starts the IFG timer. The time-out process after CRS clears is called
Carrier Deference. In the MAC, Carrier Deference has two options as selected by the bit 2-
part DefDis (TXCtl). If 2-part DefDis is clear, the two part deferral is used which meets the
requirements of ISO/IEC 8802-3 paragraph 4.2.3.2.1. As shown in the diagram, if CRS
becomes active during the first 2/3 (6.4
μ
sec) of the IFG, the MAC restarts the IFG timer. If
CRS becomes active during the last 1/3 of the IFG, the timer is not restarted to ensure fair
access to the medium.
If 2-part DefDis is set, the two part deferral is disabled. In this option, the IFG timer is allowed
to complete even if CRS becomes active after the timer has started.
The 2-part deferral has an advantage for AUI connections to either 10BASE-2 or 10BASE-5.
If the deferral process simply allowed the IFG timer to complete, then it is possible for a short
Inter Frame Gap to be generated. The 2-part deferral prevents short IFGs. The disadvantage
of the 2-part deferral is longer deferrals. In 10BASE-T systems, either deferral method should
operate about the same.
IFG Complete
CRS is Carrier Sense
When this Carrier Deference state diagram is entered from the Packet
Transmission Process, the entry m ay be to any state shown. The Packet
Transmission Process exits this state diagram ONLY from IFG Complete.
CRS changes
from 0 to 1
Line Busy
[wait for CRS to clear]
1. In this diagram, FDX (TestCTL) is clear.
Fixed
9.6 usec
IFG Delay
CRS changes
from 1 to 0
No two-part deferral
[2-part DefDis set]
Timer
complete
CRS changes
from 1 to 0 Two-part deferral used
[2-part DefDis clear]
The control bit 2-partDefDis
selects two-part deferral when
clear, and disables two-part
when set.
6.4 usec
Delay
[2/3 IFG]
If CRS goes to 1 during
the 6.4 usec timer, go back
to the Line Busy state.
Timer
complete
Fixed
3.2 usec
Delay
[1/3 IFG]
Timer complete
2. There is logic to maintain the 9.6 usec
IFG spacing between back-to-back
transmitted packets.
That logic is not shown.
NOTES: