Pwrcnt – Cirrus Logic EP93xx User Manual
Page 141
DS785UM1
5-15
Copyright 2007 Cirrus Logic
System Controller
EP93xx User’s Guide
5
5
5
RSTFLG:
Reset flag. This bit is set if the user reset button has been
pressed; forcing the RSTOn input low. It is cleared by
writing to the STFClr location. On power-on-reset, it is
reset to 0b.
TEST_RESET:
Test reset flag. This bit is set if the test reset has been
activated; it is cleared by writing to the STFClr location. On
power-on-reset, it is reset to 0b.
CLDFLG:
Cold start flag. This bit is set if the device has been reset
with a power-on-reset; it is cleared by writing to the STFClr
location. On power-on-reset, it is set to 1b.
WDTFLG:
Watchdog Timer flag. This bit is set if the Watchdog timer
resets the system. It is cleared by writing to the STFClr
location. It is reset to 0.
CHIPID:
Chip ID bits. This 8-bit register determines the Chip
Identification for the device. For the device, this value is
0x20.
CHIPMAN:
This 8-bit register determines the Chip Manufacturer ID for
the device. For the device, this value is 0x43.
PwrCnt
Address:
0x8093_0004 - Read / Write
Definition:
The PwrCnt system control register is the Clock/Debug control status register.
Bit Descriptions:
RSVD:
Reserved. Unknown During Read.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
FIR_EN
RSVD
UART
BAUD
USH_EN
DMA
M2M
CH1
DMA
M2M
CH0
DMA
M2P
CH8
DMA
M2P
CH9
DMA
M2P
CH6
DMA
M2P
CH7
DMA
M2P
CH4
DMA
M2P
CH5
DMA
M2P
CH2
DMA
M2P
CH3
DMA
M2P
CH0
DMA
M2P
CH1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSVD