Cirrus Logic EP93xx User Manual
Page 33
DS785UM1
1-5
Copyright 2007 Cirrus Logic
Introduction
EP93xx User’s Guide
1
1
1
Features of the EP93xx processors are:
• ARM920T Core:
•
200 MHz maximum run frequency and 100 MHz maximum high-speed bus frequency
for EP9302, 9307, 9312, and 9315 only
•
166 MHz maximum run frequency and 66 MHz maximum high-speed bus frequency for
EP9301 only
•
16 KByte instruction cache and 16 KByte data cache
•
Memory Management Unit (MMU) with 64-entry Translation-Lookaside-Buffers (TLBs)
enable Linux
®
and Windows
®
CE
®
• MaverickCrunch
™
Co-processor in EP9302, 9307, 9312, and 9315 only:
•
Floating point, integer and signal processing instructions
•
Optimized for digital music compression algorithms
•
Hardware interlocks allow in-line coding
• MaverickKey
™
IDs for Digital Rights Management or Design IP Security:
•
32-bit unique ID
•
128-bit random ID
• Integrated Peripherals and Interfaces:
•
EIDE, up to 2 devices in EP9312 and 9315 only
•
1/10/100 Mbps Ethernet MAC
•
Two-port USB 2.0 Full Speed host (OHCI) in EP9301 and 9302 only
•
Three-port USB 2.0 Full Speed host (OHCI) in EP9307, 9312, and 9315 only
•
IrDA controller, slow and fast mode
•
Two UARTs (16550 Type) in EP9301 and 9302 only:
•
- UART1 (optionally supports on-chip handling of HDLC)
•
- UART2 (optionally provides interface for IrDA controller)
•
Three UARTs (16550 Type) in EP9307, 9312, and 9315 only:
- UART1 and UART3 (optionally support on-chip handling of HDLC)
- UART2 (optionally provides interface for IrDA controller)
- UART3 implements both a UART and an HDLC interface identical to that of UART1;
•
LCD and Analog Raster Interface in EP9307, 9312, and 9315 only
•
2D Graphics Accelerator in EP9307and 9315 only
- Line Draw