Cirrus Logic EP93xx - Manual (Page 489)

DS785UM1 12-11
Copyright 2007 Cirrus Logic
Static Memory Controller
EP93xx User’s Guide
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Bit Descriptions:
RSVD: Reserved - Unknown During Read
IDCY: Idle Cycle - Read/Write
The value written to this field specifies the memory data
bus turnaround time between a Read access and a Write
access. The turnaround time is specified by (IDCY + 1)
HCLKs. For example, if IDCY = 0xA, the turnaround time
is 10 + 1 = 11 cycles of HCLK.
WST1: Wait States1 - Read/Write
The value written to this field specifies the ‘number of
HCLK cycles, minus 1’ that are inserted as wait cycles into
the timing for:
• A single Read or Write access, or
• The first Read or Write access of a burst-of-four
accesses.
The number of wait cycles is specified by (WST1 + 1)
HCLKs. For example, if WST1 = 0x3, 3 + 1 = 4 cycles of
HCLK are inserted into the access timing.
On reset, this field defaults to 0x1F (slowest access) to
enable booting from ROM or FLASH memory device
types.
RBLE: Read Byte Lane Enable - Read/Write
The value written to this bit specifies the output values on
the DQMn[3:0] pins during a Read access:
0 - DQMn[3:0] pins are all driven HIGH during memory
Reads (default at reset for bank 1-3,6,7)
1 - DQMn[3:0] pins are all driven LOW during memory
Reads (default at reset for bank 0)
For memory Writes, this bit must written to ‘1’.
WST2: Wait States2 - Read/Write
The value in this field specifies the ‘number of HCLK
cycles, minus 1’ that are inserted as wait cycles into the
timing for each of the 2nd, 3rd, and 4th accesses of Read
or Write burst-of-four accesses.