Cirrus Logic EP93xx - Manual (Page 702)

22-14 DS785UM1
Copyright 2007 Cirrus Logic
AC’97 Controller
EP93xx User’s Guide
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RTIS: RX Timeout Interrupt Status - If this bit is set to “1”, the
timeout FIFO interrupt is asserted.
TCIS: TX complete Interrupt Status - If this bit is set to “1”, the
transmit FIFO complete interrupt is asserted.
AC97ISRx
Address:
AC97ISR1 - 0x8088_0014 - Read Only
AC97ISR2 - 0x8088_0034 - Read Only
AC97ISR3 - 0x8088_0054 - Read Only
AC97ISR4 - 0x8088_0074 - Read Only
Definition:
Interrupt Status Register. The AC97ISR registers are the Interrupt status
registers for the controller FIFOs. All bits are cleared to zero on reset except
for the TCIS as the FIFO and shift register should both be empty.
Bit Descriptions:
RSVD: Reserved. Unknown During Read.
RIS: RX Interrupt Status - If this bit is set to “1”, the receive
FIFO interrupt is asserted.
TIS: TX Interrupt Status - If this bit is set to “1”, the transmit
FIFO interrupt is asserted.
RTIS: RX Timeout Interrupt Status - If this bit is set to “1”, the
timeout FIFO interrupt is asserted.
TCIS: TX complete Interrupt Status - If this bit is set to “1”, the
transmit FIFO complete interrupt is asserted.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD RIS TIS RTIS TCIS