Cirrus Logic EP93xx - Manual (Page 434)

10-40 DS785UM1
Copyright 2007 Cirrus Logic
DMA Controller
EP93xx User’s Guide
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The NextBuffer status bit can be used in conjunction with
the CurrentState status bits to determine the active buffer
according to the following rules:
If CurrentState[4:3] = DMA_BUF_ON and NextBuffer = 1
then Buffer0 is the active buffer.
If CurrentState[4:3] = DMA_BUF_ON and NextBuffer = 0
then Buffer1 is the active buffer.
If CurrentState[4:3] = DMA_BUF_NEXT and NextBuffer =
0 then Buffer0 is the active buffer.
If CurrentState[4:3] = DMA_BUF_NEXT and NextBuffer =1
then Buffer1 is the active buffer.
DREQS: DREQ Status - This bit reflects the status of the
synchronized external DMA Request signal or IDE/SSP
requests:
0 - No external DMA request is pending or, in the case of a
transfer without handshaking, the request is not validated
yet, the wait state counter is running.
1 - An external DMA request or a validated IDE/SSP or
external peripheral without handshaking request is
pending.
DREQS can be polled by software at any time. It can, for
example, be used to determine whether or not the DMA
needs to be set up for a transfer when the DMA is in the
STALL state and is receiving DREQs, but the BCRx
registers have not been programmed. It is important to
notice that, in the case of a transfer without handshaking
(external DMA or IDE or SSP), DREQS might be clear if a
request is pending but is not validated as a result of a wait
state counter still running.
When the channel STATUS register is written with any 32-
bit value, this will cause the DREQS bit of the STATUS
register to be cleared. A write to the STATUS register only
affects the DREQS bit. If an edge is detected on DREQ
when no previous request is still pending in the DMA (that
is, DREQS clear), then the DREQS bit is set by the DMA