Cirrus Logic EP93xx - Manual (Page 176)

6-14 DS785UM1
Copyright 2007 Cirrus Logic
Vectored Interrupt Controller
EP93xx User’s Guide
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6
6
Definition:
Protection Enable Register. The VICxProtection register enables or disables
protected register access. If the bus master cannot generate accurate
protection information, leave this register in its reset state to allow User mode
access.
Bit Descriptions:
RSVD: Reserved. Unknown During Read.
Protection: Enables or disables protected register access. When
enabled, only Privileged mode accesses (reads and
writes) can access the interrupt controller registers. When
disabled, both User mode and Privileged mode can
access the registers. This bit is cleared to ‘0’ on reset, and
can only be accessed in Privileged mode.
VICxVectAddr
Address:
VIC1VectAddr: 0x800B_0030 - Read/Write
VIC2VectAddr: 0x800C_0030 - Read/Write
Definition:
Vector Address Register. The VICxVectAddr register contains the Interrupt
Service Routine (ISR) address of the currently active interrupt.
Note: Reading from this register provides the address of the ISR, and indicates to the priority
hardware that the interrupt is being serviced. Writing to this register indicates to the
priority hardware that the interrupt has been serviced. The register should be used as
follows:
• The ISR reads the VICxVectAddr register when an IRQ interrupt is generated
• At the end of the ISR, the VICxVectAddr register is written with any value in order to
update the priority hardware.
Reading or writing to the register at other times can cause incorrect operation.
Note: If you are using the VIC and a program/debugger ever reads address VIC_BASE + 0x30,
a value must be written to VIC_BASE + 0x30. If not, only higher priority interrupts are
enabled and there are no higher priority interrupts. Therefore, no more interrupts will
occur. If you use the VIC in Vectored Interrupt mode, this is not an issue.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VectorAddr
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VectorAddr