Rockwell Automation 21G PowerFlex 750-Series AC Drives Programming Manual - Manual (Page 120)

120 Rockwell Automation Publication 750-PM001J-EN-P - October 2014
Chapter 3 Drive Port 0 Parameters
Fil
e
Gr
ou
p
No. Display Name
Full Name
Description Values
Re
ad
-Write
Da
ta T
ype
SPEED C
O
NTROL
Speed Re
gula
to
r
635 Spd Options Ctrl
Speed Options Control RW 16-bit
Integer
Configures options related to Speed Control as follows:
Bit 0 “Ramp Hold” – The output of the speed reference ramp will stop changing and hold its output constant while this bit is set. When this bit is clear, the ramp
output will be allowed to change. If this bit becomes set while P594 [Ramped Spd Ref] is in the S Curve region, the S Curve will be allowed to complete before the
output is held.
Bit 1 “Ramp Disable” – When set, the speed reference ramp will be bypassed. P594 [Ramped Spd Ref] will track the ramp input.
Bit 2 “StpNoSCrvAcc” – There are some conditions where the drive may continue to accelerate briefly following a request to stop. This will occur if the drive was in
the process of accelerating on an S Curve when the stop request occurred. This bit enables an option to discontinue acceleration immediately when the stop request
occurs. The S Curve profile that was in process will then change to a linear decel ramp.
Bit 3 “SpdRegIntRes” – When set, the P654 [Spd Reg Int Out] which is the output of the Vector mode speed regulator’s integral term will be forced to zero. The same
result can be achieved by setting the regulator’s integral gain to zero.
Bit 4 “SpdRegIntHld” – When set, the P654 [Spd Reg Int Out] which is the output of the Vector mode speed regulator’s integral term will stop changing and be held
constant. Other conditions in the drive such as a limit condition in P945 [At Limit Status] may have the same result.
Bit 5 “SpdErrFilter” – When set, the speed error filter in the drive’s Vector mode speed regulator will be configured for a single stage low pass filter. When clear, the
error filter will be configured for a two stage low pass filter. The two stage configuration is the normal or default setting for the error filter.
Bit 6 “Jog No Integ” – When set, the P654 [Spd Reg Int Out] which is the output of the Vector mode speed regulator’s integral term will be forced to zero while
jogging.
Bit 7 “Auto Tach SW” – This bit is used to enable the Automatic Tach Switchover feature. This feature is used to switch motor velocity feedback sources from the
Primary (P125) to Alternate (P128) source in the event that the primary source fails. This switchover can take place while the drive is running. The P936 [Drive
Status 2] Bit 5 “FdbkLoss SwO” will indicate clear when the Primary source is active and set when the alternate source is active.
• When using the Automatic Tach Switchover feature, the Feedback Loss Configuration parameter on the feedback module should be set to something other than
fault.
• When using induction motors, clearing this bit when the alternate source is active will restore control to the Primary source, provided that the primary source is
functioning.
• When using permanent magnet motors, cycling power to the drive will restore control to the Primary source, provided that the primary source is functioning. If
this bit remains off, then the Automatic Tach Switchover feature will be disabled.
Important: The Primary feedback source uses the P126 [Pri Vel FdbkFltr] filter setting and tuning gains set in P636 [Speed Reg BW], P645 [Speed Reg Kp], and
P647 [Speed Reg Ki]. The Alternate feedback sources uses the P129 [Alt Vel FdbkFltr] filter setting and tuning gains set in P648 [Alt Speed Reg BW], P649 [Alt Speed
Reg Kp], and P650 [Alt Speed Reg Ki].
Bit 8 “Delayed Ref” – When this bit is set, an additional processor scan delay period is inserted between the P594 [Ramped Spd Ref] and the input to the Speed
Reference filter. This delay is intended to be used in applications where multiple, coordinated drives are used. A drive that supplies the speed reference for use by
other drives to follow would typically use this delay. The delay would allow time for the speed reference to reach the other units before it is acted upon by the
sourcing unit, thereby synchronizing the speed reference among all units. When this bit is clear, no speed reference delay is inserted.
636 Speed Reg BW
Speed Regulator Bandwidth
Sets the speed loop bandwidth and determines the dynamic behavior of the speed loop.
As bandwidth increases, the speed loop becomes more responsive and can track a faster
changing speed reference. A change to this parameter will cause an automatic update of
P645 [Speed Reg Kp], P647 [Speed Reg Ki] and P644 [Spd Err Fltr BW]. The configuration
settings for Inertia Adaption (product dependent) will also be automatically selected
when this feature is enabled. To disable the automatic gain and filter update, set this
parameter to a value of zero.
The maximum allowable value of this parameter will be limited by the ratio of P646
[Speed Reg Max Kp] to P76 [Total Inertia], and the type of speed feedback source in use
(encoder vs. open loop). For operation following an Automatic Tach Switchover, the
bandwidth specified in P648 [Alt Speed Reg BW] will be used. Units:
Default:
Min/Max: R/S
Calculated
0.00 / Calculated RW Real
Options
Res
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Res
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Res
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Res
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Res
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Res
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Res
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De
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SW
Jo
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SpdE
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ilt
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SpdRegIn
tHld
SpdRegIn
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St
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Cr
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Ram
p Dis
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Ra
mp Hol
d
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 = False
1 = True