Rockwell Automation 21G PowerFlex 750-Series AC Drives Programming Manual - Manual (Page 268)

268 Rockwell Automation Publication 750-PM001J-EN-P - October 2014
Chapter 5 Embedded Feature and Option Module Parameters
Single
Increm
ent
al
Encode
r
5 Encoder Status
Encoder Status RO 16-bit
Integer
Status information for the Incremental Encoder Module.
Bit 0 “Z Chan Enbl” – State of the corresponding bit in the [Encoder Cfg] parameter.
Bit 1 “A Chan Only” – State of the corresponding bit in the [Encoder Cfg] parameter.
Bit 2 “A Input” – State of encoder A input signal.
Bit 3 “A Not Input” – State of encoder A Not input signal.
Bit 4 “B Input” – State of encoder B input signal.
Bit 5 “B Not Input” – State of encoder B Not input signal.
Bit 6 “Z Input” – State of encoder Z input signal.
Bit 7 “Z Not Input” – State of encoder Z Not input signal.
Bit 8 “Marker Event” – When channel Z (marker pulse) is used, indicates that a marker pulse is detected. Automatically cleared in the homing routine or due to
clearing of faults. This bit will remain on until cleared by either the homing function, spindle orient function or clear fault. For the Single and Dual Incremental
encoder options, the marker input can only be used by the homing and spindle orient functions. Clearing the encoder faults will also clear the Marker Event status.
The single and dual encoder cards use the same clear fault mechanism that is used to clear the drive faults.
Bit 9 “Inv Home In” – State of the corresponding bit in the [Encoder Cfg] parameter. When set, the home input signal will be inverted.
Bit 10 “Home Input” – Active state of the Home Input signal. This status bit gets inverted if the “Inv Home In” bit is enabled.
Bit 11 “HomeIn Armed” – Indicates that the homing logic is configured to latch the encoder position upon the next transition of the home input.
Bit 12 “HomeIn Event” – Indicates that the homing logic has latched the encoder position in response to a transition of the home input.
Bit 13 “HomMrk Armed” – Indicates that the homing logic is configured to latch the encoder position upon the next marker (Z channel) pulse.
Bit 14 “HomMrk Event” – Indicates that the homing logic has latched the encoder position in response to a marker (Z channel) pulse.
Bit 15 “Direction” – State of the corresponding bit in the [Encoder Cfg] parameter.
6 Error Status
Error Status RO 16-bit
Integer
Status information that will result in a feedback loss condition.
Bit 0 “Open Wire” – Indicates that an input signal (A, B or Z) is in the same state as its complement (A Not, B Not, Z Not). For open wire detection to work, the
encoder signals must be differential (not single ended). The Z channel is only checked when enabled. See P1 [Encoder Cfg].
Bit 1 “Phase Loss” – Indicates that more than 30 phase loss (open wire) events have occurred over an 8 msec time period. The same restrictions apply as on [Encoder
Cfg] Bit 0. The Z channel will be ignored if not enabled. Checking for phase loss on the Z channel is only done when the Z channel is enabled.
Bit 2 “Quad Loss” – Quadrature loss events occur when simultaneous edge transitions occur on both the A and B encoder channels. Indicates that more than 10
quad loss events over a 8 msec time period are detected. Only valid when both A and B channels are used (not 'A Chan Only' in [Encoder Cfg]).
Bit 15 “SI Comm Loss” – Indicates a communication loss between the main control board and the encoder module over the Serial Interface backplane.
Fi
le
Grou
p
No. Display Name
Full Name
Description Values
Re
ad
-W
ri
te
Da
ta
T
ype
Options
Dir
ec
tion
HomMrk E
vent
HomMrk A
rme
d
HomeIn E
vent
HomeIn Armed Home Input In
v Hom
e In
Ma
rk
er E
vent
Z Not
In
pu
t
Z In
put
B N
ot In
put
B Input A Not
Input
A Inpu
t
A Chan O
nly
Z Ch
an
En
bl
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 = Condition False
1 = Condition True
Options
SI C
omm
Lo
ss
Re
ser
ved
Re
ser
ved
Re
ser
ved
Re
ser
ved
Re
ser
ved
Re
ser
ved
Re
ser
ved
Re
ser
ved
Re
ser
ved
Re
ser
ved
Re
ser
ved
Re
ser
ved
Qu
ad
L
os
s
Phase L
oss
Op
en
W
ire
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 = Condition False
1 = Condition True