Rockwell Automation 21G PowerFlex 750-Series AC Drives Programming Manual User Manual
Page 288
288
Rockwell Automation Publication 750-PM001J-EN-P - October 2014
Chapter 5
Embedded Feature and Option Module Parameters
Univ
ersal
F
eedback
Regi
st
rati
on
94
Rgsn Sts
Registration Status
RO
16-bit
Integer
Status of the configured registration events.
100
103
106
109
112
115
118
121
124
127
Rgsn Latch1 Cfg
Rgsn Latch2 Cfg
RO
16-bit
Integer
Rgsn Latch3 Cfg
Rgsn Latch4 Cfg
Rgsn Latch5 Cfg
Rgsn Latch6 Cfg
Rgsn Latch7 Cfg
Rgsn Latch8 Cfg
Rgsn Latch9 Cfg
Rgsn Latch10 Cfg
Registration Latch n Configure
Configures Registration Latch n.
The registration function consists of 10 sets of latches. The latched data includes a feedback position and associated time parameter. Time is relative to when the
feedback devices were last sampled. Once the registration function has been armed, the values for these parameters are captured (latched) upon the occurrence of
a trigger event. See functionality tables on following page.
The registration trigger for each latch is separately configured by its Latch Configuration Parameter. Refer to
. The trigger logic includes two
separate trigger stages. Each trigger stage is separately configured to use one of three possible registration input signals or the marker (Z pulse) of the selected
feedback channel. Trigger combination logic determines how the two stages are combined to define the trigger event conditions.
Bit 0 “Channel Sel” – Channel select (FB0 or FB1).
Bit 1 “Fwd Capture” – Direction select forward.
Bit 2 “Rev Capture” – Direction select reverse.
Bit 3 “Stg1 In b0” – Latch stage 1 input selection b0
Bit 4 “Stg1 In b1” – Latch stage 1 input selection b1
Bit 6 “Stg1EdgeRise” – Latch stage 1 edge/level select: Rising edge or high level
Bit 7 “Stg1EdgeFall” – Latch stage 1 edge/level select: Falling edge or low level
Bit 8 “Logic Sel b0” – Trigger stage combination logic
Bit 9 “Logic Sel b1” – Trigger stage combination logic
Bit 10 “Stg2 In b0” – Latch stage 2 input selection b0
Bit 11 “Stg2 In b1” – Latch stage 2 input selection b1
Bit 13 “Stg2EdgeRise” – Latch stage 2 edge/level select: Rising edge or high level
Bit 14 “Stg2EdgeFall” – Latch stage 2 edge/level select: Falling edge or low level
Fi
le
Grou
p
No.
Display Name
Full Name
Description
Values
Re
ad
-W
ri
te
Da
ta
T
ype
Options
Home Input
Rgsn Input
1
Rgsn Input
0
Re
ser
ve
d
Re
ser
ve
d
Re
ser
ve
d
Re
ser
ve
d
Re
ser
ve
d
Re
ser
ve
d
Re
ser
ve
d
Re
ser
ve
d
Re
ser
ve
d
La
tc
h10F
ou
nd
La
tc
h10A
rmed
La
tc
h9 F
ound
La
tc
h9 Armed
La
tc
h8 F
ound
La
tc
h8 Armed
La
tc
h7 F
ound
La
tc
h7 Armed
La
tc
h6 F
ound
La
tc
h6 Armed
La
tc
h5 F
ound
La
tc
h5 Armed
La
tc
h4 F
ound
La
tc
h4 Armed
La
tc
h3 F
ound
La
tc
h3 Armed
La
tc
h2 F
ound
La
tc
h2 Armed
La
tc
h1 F
ound
La
tc
h1 Armed
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0 = False
1 = True
Options
Res
er
ve
d
St
g2E
dgeF
all
St
g2E
dgeRise
Res
er
ve
d
St
g2 In b1
St
g2 In b0
Lo
gic Sel
b1
Lo
gic Sel
b0
St
g1E
dgeF
all
St
g1E
dgeRise
Res
er
ve
d
St
g1 In b1
St
g1 In b0
Rev C
aptur
e
Fw
d C
aptur
e
Ch
annel Sel
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0 = Condition False
1 = Condition True