Rockwell Automation 21G PowerFlex 750-Series AC Drives Programming Manual - Manual (Page 142)

142 Rockwell Automation Publication 750-PM001J-EN-P - October 2014
Chapter 3 Drive Port 0 Parameters
POSITION
CONTROL
Po
in
t t
o Po
in
t
786 PTP Rev Vel Lmt
Point-To-Point Reverse Velocity Limit
Provides the maximum reverse speed reference limit from the PTP regulator. Units
Default:
Min/Max:
Hz
RPM
P27 [Motor NP Hertz] x 0.5
P28 [Motor NP RPM] x 0.5
0.00/P27 [Motor NP Hertz]
0.00/P28 [Motor NP RPM] RW Real
787 PTP S Curve
Point-To-Point S Curve
Provides the amount of time that is applied to the S Curve from the PTP regulator. Units:
Default:
Min/Max: Secs
0.500
0.000 / 4.000 RW Real
788 PTP Vel Override
Point-To-Point Velocity Override
Provides multiplier to both forward P785 [PTP Fwd Vel Lmt] and reverse P786 [PTP Rev
Vel Lmt] speed limits. This parameter applies to the speed limits when the override bit
P770 [PTP Control] Bit 0 “Vel Override” is on. Default:
Min/Max: 1.00
0.20 / 1.50 RW Real
789 PTP EGR Mult
Point-To-Point Electronic Gear Ratio Multiply
EGR multiplier (numerator) for position index output. The output applies to the point-
to-point command P784 [PTP Command]. Default:
Min/Max: 1
–/+2000000 RW 32-bit
Integer
790 PTP EGR Div
Point-To-Point Electronic Gear Ratio Divide
EGR divider (denominator) for position index output. The output applies to the point-to-
point command P784 [PTP Command]. Default:
Min/Max: 1
1 / 2000000 RW 32-bit
Integer
Fi
le
Grou
p
No. Display Name
Full Name
Description Values
Re
ad
-W
ri
te
Da
ta
T
ype
Fil
e
Gr
ou
p
No. Display Name
Full Name
Description Values
Re
ad
-Write
Da
ta
T
yp
e
POSITION
CONTROL
Ph
as
e Lo
ck
Lo
op
795 PLL Control
Phase Locked Loop Control
RW 16-bit
Integer
Sets bits to configure the phase locked loop control.
Bit 0 “PLL Enable” – enables the phase locked loop control.
Bit 1 “Velocity FF” – enables the velocity feed forward path.
Bit 2 “Ext Vel FF” – enables the external velocity feed forward through the PLL external speed reference selected by the PLL external speed selection P796 [PLL Ext
Spd Sel].
Bit 3 “Accel Comp” – enables providing an element of acceleration compensation to the feed forward branch. This is not recommended for use with external inputs
because of increased noise.
Bit 4 “PCAM Enable” – enables PCAM function with the PLL function.
Bit 5 “PTP Enable” – enables point-to-point function with the PLL function.
Bit 6 “Prof Enable” – enables profiler function with the PLL function.
Only bits 4, 5, and 6 allow associating with the PLL function.
796 PLL Ext Spd Sel
Phase Locked Loop External Speed Select
Selects an external speed reference source.
Default:
Options: 797
1 / 159999 RW 32-bit
Integer
755
Options
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Pro
f En
ab
le
PTP
En
ab
le
PC
AM
En
ab
le
Ac
ce
l Co
m
p
Ex
t V
el
FF
Ve
lo
ci
ty
F
F
PL
L En
ab
le
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 = False
1 = True
755