Comtech EF Data CDM-570A - Manual (Page 37)

CDM-570A/570AL Satellite Modem with Optional Packet Processor MN-CDM570A
Introduction Revision 2
1–3
Transmit data is received by the terrestrial interface where line receivers convert the clock and
data signals to CMOS levels for further processing. A small FIFO follows the terrestrial interface
to facilitate the various clocking and framing options. If framing is enabled, the transmit clock
and data output from the FIFO pass through the framer, where the EDMAC overhead data is
added to the main data; otherwise, the clock and data are passed directly to the Forward Error
Correction encoder.
In the FEC encoder, the data is differentially encoded, scrambled, and then convolutionally
encoded. Following the encoder, the data is fed to the transmit digital filters, which perform
spectral shaping on the data signals. The resultant I and Q signals are then fed to the BPSK,
QPSK/OQPSK, 8-PSK, or 16-QAM modulator. The carrier is generated by a frequency synthesizer,
and the I and Q signals directly modulate this carrier to produce an IF output signal.
In both L-Band and 70/140 MHz operation, receive signals are first converted to a UHF
frequency for SAW filtering, and are then down converted to a lower IF frequency for direct
sampling in a high speed A/D converter. An AGC circuit controls the signal level presented to the
A/D converter. Digital signal processing performs the final quadrature conversion to baseband
followed by Nyquist filtering, carrier recovery, and symbol timing recovery. The resultant
demodulated signal is fed, in soft decision form, to the selected FEC decoder (which can be
Viterbi, TCM, Reed-Solomon, or Turbo if installed).
After decoding, the recovered clock and data pass to the de-framer (if EDMAC framing is
enabled) where the overhead information is removed. Following this, the data either passes or
bypasses the Plesiochronous/Doppler buffer, which has a programmable size. From here, the
receive clock and data signals are routed to the terrestrial interface, and are passed to the
externally connected DTE equipment.
The modem signal processing functions are performed in a single, large Field-Programmable
Gate Array (FPGA), which permits rapid implementation of changes, additions and
enhancements in the field. These signal processing functions are controlled and monitored by a
32-bit RISC microprocessor, which also controls all front panel, serial and Ethernet interfaces.