Altera Stratix GX Transceiver - Manual (Page 102)

4–20 Altera Corporation
Stratix GX Transceiver User Guide January 2005
SONET Mode Clocking
Stratix GX logic array clock usage can be reduced by using the IQ lines.
The IQ lines are used when a refclkb input port from one transceiver
block or channel drives any other transceiver blocks or channels. The
Quartus II software automatically determines the IQ line usage.
When determining the location of refclkb pins, be sure to take into
consideration what is fed by the pin you choose.
Table 4–3 shows the
available IQ lines and which transceiver block refclkb drives them.
This capability is based on the number of transceiver channels in the
Stratix GX device.
Figure 4–15 shows the transceiver routing with respect to inter-
transceiver lines. It is important to use this information when placing
REFCLKB
pins. For example, if a REFCLKB pin is required to feed a
transmitter PLL using an IQ line, the REFCLKB pin cannot be in
transceiver block 1, because IQ2 only feeds the receiver PLLs.
Table 4–3. REFCLKB to Inter-Transceiver Line Connections
Channel Density
REFCLKB in
Transceiver Block
Number
Channels in
Transceiver Block
IQ Line Driven by
REFCLKB
8 channels
(EP1S10) 0 [3:0] IQ2
1 [7:4] IQ0
16 channels
(EP1S25) 0 [3:0] N/A
1 [7:4] IQ2
2 [11:8] IQ0
3 [15:12] IQ1
20 channels
(EP1S40) 0 [3:0] N/A
1 [7:4] IQ2
2 [11:8] IQ0
3 [15:12] IQ1
4 [19:16] N/A