Altera Stratix GX Transceiver User Manual

Page 74

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3–28

Altera Corporation

Stratix GX Transceiver User Guide

January 2005

Basic Mode Clocking

Figure 3–24

shows the transceiver routing with respect to inter-

transceiver lines for the EP1SGX40G Device. This device has an extra
transceiver block (4), which is in the middle of the row of transceiver
blocks. This information is important when placing REFCLKB pins. For
example, if a REFCLKB pin must feed a transmitter PLL using an inter-
transceiver line, the REFCLKB pin cannot be in transceiver block 1,
because IQ2 feeds only the receiver PLLs. REFCLKB is used for
transceiver block 2 and transceiver block 3.

Figure 3–24. Inter-Transceiver Line Connections for the EP1SGX40G Device

PLD

Global

Clocks

IQ0

IQ1

IQ2

Transceiver Block 2

TX PLL

IQ0
IQ1