Altera Stratix GX Transceiver - Manual (Page 23)

Altera Corporation 2–5
January 2005 Stratix GX Transceiver User Guide
Stratix GX Analog Description
As with the V
OD
settings, you can set the pre-emphasis settings statically
during configuration or adjust them dynamically in user mode. You can
set the static pre-emphasis value through a drop-down menu in the
altgxb
MegaWizard Plug-In, which sets the appropriate pre-emphasis
setting in the configuration file. The disadvantage of the static mode
setting is that the pre-emphasis is set on a per-transceiver-block basis and
cannot be changed without regenerating another programming file.
On the other hand, if you select dynamic adjustment in the altgxb
MegaWizard Plug-In, the pre-emphasis setting can be configured
dynamically by the device during user mode. This configuration is done
by asserting encoded values on the tx_preemphasisctrl bus, which
is instantiated in the altgxb module when you select the dynamic
adjustment option. This option lets you make quick performance
evaluations of the various settings without having to recompile and
regenerate multiple configuration files. Another advantage of this option
is that it allows the pre-emphasis of each channel to be configured
independently. For further details, refer to
“MegaWizard Analog
Features” on page 2–20 .
Avoid pre-emphasis and V
OD
settings that yield a value greater than
1,600 mV. Settings beyond this value do not damage the buffer, but they
prevent accurate device operation. Verify that the combination of V
OD
and pre-emphasis settings do not exceed the 1,600-mV limit.
Programmable Transmitter Termination
The Stratix GX transmitter buffer includes a 100-, 120-, or 150-
Ω
programmable on-chip differential termination resistor. The Stratix GX
transmitter buffers are current-mode drivers, so the resultant V
OD
is a
function of the transmitter termination value. For more information on
resultant V
OD
values, see “Programmable Voltage Output Differential
(V
OD
)” on page 2–3 .
Transmitter PLL
Each transceiver block contains a transmitter PLL and a slow-speed
reference clock. The transmitter PLL receives the reference clock and
generates the high-speed serial clock used by the serializer. The slow-
speed reference clock is used for the transceiver logic.
Figure 2–4 shows
the transmitter PLL’s block diagram. The pll_locked signal indicates
when the transmitter PLL is locked to the reference clock. A high signal
indicates that the PLL is locked to the reference clock; a low signal
indicates that the PLL is not locked to the reference clock.