Altera Stratix GX Transceiver - Manual (Page 36)

2–18 Altera Corporation
Stratix GX Transceiver User Guide January 2005
Receiver Analog
or not the CRU is ready. When both signals are asserted, the
rx_locktodata[]
signal takes precedence over the
rx_locktorefclk[] signal.
You might want to have control over both rx_locktorefclk[] and
rx_locktodata[]
signals to potentially reduce the CRU lock times.
The PPM threshold frequency detector and phase relationship detector
require additional latencies to ensure that the CRU is ready to lock to
data. These extra latencies are potentially reduced by manually
controlling the CRU train signals. You assert the rx_locktorefclk[]
signal to initially train the CRU and, after some delta time, assert the
rx_locktodata[]
signal.
You configure the controller that controls the signals based on your
system. You do this by experimenting because many variables must be
considered, such as temperature, transition densities, and data rates.
However, by doing so, you are not subjected to the CRU lock times
required to verify if the two conditions to switch from lock-to-reference
mode to lock-to-data mode in the defaulted automatic mode are met.
When the rx_locktorefclk goes high, the rx_freqlocked signal is
ignored and does not toggle. The rx_freqlocked signal always goes
high if lock-to-data mode is asserted. If you want to transition from
lock-to-data mode to automatic mode, the transition should be followed
by rx_analogreset to send the rx_freqlocked signal low. The CRU
does not often transition from manual mode to automatic mode during
system operation.
1 The rx_analogreset signal functions like a power down
signal as opposed to a digital reset. For more information on
various reset signals, refer to the chapter Reset Control & Power
Down.
Run Length Violation Detection Circuit
The programmable run length violation (RLV) circuit is in the CRU and
detects consecutive ones or zeros in the data. If the data stream exceeds
the preset maximum number of consecutive ones or zeros, the violation is
signified by the assertion of the rx_rlv signal.
The rx_rlv signal is not synchronized to the parallel data, and as a result
appears in the logic array earlier than the run-length violation data. To
ensure that the FPGA latches this signal in systems where there are
frequency variations between the recovered clock and the PLD logic array
clock, the rx_rlv signal is asserted for more than two clock cycles in 8-
or 10-bit data modes and three clock cycles in 16- or 20-bit data modes.