Altera Stratix GX Transceiver - Manual (Page 266)

9–40 Altera Corporation
Stratix GX Transceiver User Guide January 2005
Recommended Resets
■ In this example, whenever the rx_freqlocked signal toggles the
rxdigitalreset
, the receiver’s digital circuit is reset. However,
you can make changes to the design to avoid this if, for example, you
want to debug your design without the core being reset.
■ If you plan to use REFCLKB pins in your design, see Appendix C,
REFCLKB Pin Constraints for information about the effects of analog
resets (pll_arest, rx_analogreset).
/*
Copyright (c) Altera Corporation, 2004.
This file may contain proprietary and confidential information of
Altera Corporation
Contacting Altera
=================
We have made every effort to ensure that this design example works
correctly. If you have a question that is not answered by the
information then please contact Altera Support.
****************************************************************
Reset Sequence for the ALTGXB. The configuration of GXB for which
the following
reset sequence is valid is:
Transmit and Receive : Receiver ONLY
Datapath : Single Width(8/10 bits) or Double Width (16/20
bits)
receive parallel clock: rx_clkout
Functional Mode :'Any'
RX PLL CRU : Train RX PLL CRU with TX PLL ouput clock (refClk
as shown in Mega Wizard)
***************************************************************/
`timescale 1ns/10ps
module reset_seq_rx_ONLY_TXPLL_rx_clkout (
rx_clkout,
inclk,
sync_reset,
async_reset,
receive_digitalreset,
pll_locked,
rx_freqlocked,
pll_areset,
rxanalogreset,
rxdigitalreset
);
input inclk; //GXB input reference clock
input rx_clkout;//Receive recovered clock