Altera Stratix GX Transceiver - Manual (Page 269)

Altera Corporation 9–43
January 2005 Stratix GX Transceiver User Guide
Reset Control & Power Down
waitstate_timer <= waitstate_timer -
1'b1 ;
rxdigitalreset_inclk<= 1'b1;
rxanalogreset_inclk <= 1'b0;
pll_areset <= 1'b0;
end
else
begin
state <= STABLE_TX_PLL;
rxdigitalreset_inclk<= 1'b1;
rxanalogreset_inclk <= 1'b0;
pll_areset <= 1'b0;
end
WAIT_STATE: if (sync_reset) //Synchronous Reset can be
asserted in IDLE state (After reset seq has finished)
begin
rxdigitalreset_inclk <= 1'b1;
rxanalogreset_inclk <= 1'b1;
pll_areset <= 1'b1;
state <= STROBE_TXPLL_LOCKED;
end
else if(rx_freqlocked) //Condition to have
rx_freqlocked signal a stable high and should not bounce around
begin
//Decrement a Timer of 2ms (Refer
Stratix GX Datasheet for accurate value)after rx_freqlocked is
asserted
//This time is given to ensure the
recovered clock to be stable (Cannot have any freq variations) and
is locked to incomming data
if(waitstate_timer == 0)
begin
state <= IDLE;
rxdigitalreset_inclk<= 1'b0;
rxanalogreset_inclk <=
1'b0;
pll_areset <= 1'b0;
end
else
begin
waitstate_timer <=
waitstate_timer - 1'b1;
rxdigitalreset_inclk<= 1'b1;
rxanalogreset_inclk <=
1'b0;
pll_areset <= 1'b0;
state <= WAIT_STATE;
end
end
else
begin
rxdigitalreset_inclk<= 1'b1;
rxanalogreset_inclk <= 1'b0;