Altera Stratix GX Transceiver - Manual (Page 32)

2–14 Altera Corporation
Stratix GX Transceiver User Guide January 2005
Receiver Analog
where the reference clock signal is divided by 2, yielding a 311 MHz clock
at the PFD. This 311-MHz reference clock is then multiplied by a factor of
8 to achieve the 2,488-MHz clock at the VCO.
If the reference clock (RX_CRUCLK) exceeds 325 MHz, the clock must be
fed by the dedicated local reference clock pin, REFCLKB. By default, the
Quartus II software assigns pins to be LVTTL, so a 1.5-V PCML I/O
standard assignment is required to select the REFCLKB port as the
reference source. The Quartus II software prompts a fitter error if the
reference clock exceeds 325 MHz and the reference clock source is not on
the REFCLKB port.
The pre-divider on the REFCLKB path is also used to support additional
multiplication factors. The block diagram in
Figure 2–10 on page 2–13
shows that /m supports only multiplication factors of 8, 10, 16, and 20,
but
Table 2–4 states that the additional multiplication factors of 2, 4, and
5 can also be achieved.
Without using the transmitter PLL, the pre-divider achieves the
multiplication factors of 4 and 5. A multiplication factor of 4 is achieved
by pre-dividing the reference clock by 2 and then multiplying the
resulting frequency by 8, which yields a multiplication factor of 4. A
multiplication factor of 5 is achieved in the same manner by pre-dividing
the reference clock by 2 and then multiplying the resulting frequency by
10, which yields a multiplication factor of 5.
The MegaWizard Plug-In altgxb option enables the transmitter PLL in
receiver mode. There is also an option to train the receiver CRU with the
output of the low-speed transmitter PLL clock. If you select this option,
all the multiplication factors that are supported in the transmitter PLL are
also supported in the receiver CRU PLL, including the multiplication
factor of 2. This option selects the low-speed transmitter PLL clock as the
reference source. The low speed transmitter PLL clock is either divided by
a SERDES factor of 8 or 10. The receiver PLL then multiplies this reference
clock by a factor of 8 or 10 to achieve the same multiplication factor as the
transmitter PLL.
For example, a multiplication factor of 2 is achieved on the transmitter
PLL by pre-dividing the reference clock by 2 and then multiplying the
resultant frequency by 4, which yields a multiplication factor of 2.
However, on the low-speed clock output, this frequency is divided by a
factor of 8 or 10, depending on the deserialization factor. The low-speed
clock feeds the reference of the receiver PLL where the clock is multiplied
back up by a factor of 8 or 10, which results in total multiplication factor
of 2.