Altera Stratix GX Transceiver - Manual (Page 261)

Altera Corporation 9–35
January 2005 Stratix GX Transceiver User Guide
Reset Control & Power Down
/*
Copyright (c) Altera Corporation, 2004.
This file may contain proprietary and confidential information of
Altera Corporation
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We have made every effort to ensure that this design example works
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****************************************************************
Reset Sequence for the ALTGXB. The configuration of GXB for which
the following
reset sequence is valid is:
Transmit and Receive : Receiver ONLY
Datapath : Single Width(8/10 bits) or Double Width
(16/20 bits)
receive parallel clock: rx_coreclk
Functional Mode :'Any'
RX PLL CRU : Train RX PLL CRU with TX PLL ouput clock
(refClk as shown in Mega Wizard)
***************************************************************/
`timescale 1ns/10ps
module reset_seq_rx_ONLY_TXPLL_rx_coreclk (
rx_coreclk,
inclk,
sync_reset,
async_reset,
receive_digitalreset,
pll_locked,
rx_freqlocked,
pll_areset,
rxanalogreset,
rxdigitalreset
);
input inclk; //GXB input reference clock
input rx_coreclk;//Receive recovered clock
input sync_reset; //Input: synchronous reset from the system
input async_reset; //Input: async reset from system
input receive_digitalreset; //Input : Reset the receiver section
input rx_freqlocked; //rx_freqlocked signal from receive;
Transition from 'lock to reference clock mode' to 'lock to data
mode'
input pll_locked; // Transmit PLL of GXB locked