Altera Stratix GX Transceiver - Manual (Page 175)

Altera Corporation 6–21
January 2005 Stratix GX Transceiver User Guide
GigE Mode
Figure 6–21 shows the altgxb megafunction configured so that the
training receiver PLL with the transmitter PLL is enabled. The transmitter
PLL is fed from an inclk port that can, in turn, be fed from a dedicated
REFCLKB
, global clock, regional clock, or fast regional clock source. The
receiver logic is clocked by the recovered clock from the clock recovery
unit up to the deskew FIFO buffer in the data path. Rate matching occurs
between the recovered clock of the channel and refclk from the
transmitter PLL. The data from the receiver’s parallel interface is clocked
by coreclk_out from the transmitter PLL. On the transmitter channel,
the output of the transmitter PLL, coreclk_out, is sent from the logic
array as an output and also loops back to clock the write side of the
transmit phase compensation FIFO buffer (in this case, software
automatically routes the connection) and the read side of the receive
phase compensation FIFO buffer.
The training receiver PLL clock recovery unit (CRU) clock from the
transmitter PLL can be disabled in the altgxb MegaWizard tool.
Deselecting this option adds an additional RX_CRUCLK input reference
clock port for the receiver PLL. This feature supports additional
multiplication factors for the receiver PLL and also enables the separation
of receiver and transmitter reference clocks. This configuration is shown
in
Figure 6–22 .
f
For more information on parallel interface speeds, refer to the Stratix GX
FPGA Family data sheet.