Altera Stratix GX Transceiver - Manual (Page 136)

5–24 Altera Corporation
Stratix GX Transceiver User Guide January 2005
XAUI Mode Clocking
An example is the invalid encoding of a K24.1 (data = 8'h38 +
tx_ctrlenable
= 1'b1). Depending on the current running disparity,
you can encode the K24.1 to be 10'b0110001100 (0x18C), which is
equivalent to a D24.6+ (0xD8 from the RD+ column). An 8B/10B decoder
decodes this value incorrectly (based on the 8B/10B Fibre Channel
specification).
XAUI Mode
Clocking This section describes the clocking supported by the Stratix GX device in
XAUI mode.
XAUI Mode Channel Clocking
This section describes clocking of the transceiver, internal clocking
details, and external clock ports in XAUI mode. Each block diagram
shows the input and output port clocks. Most of the settings are based on
per transceiver block (4 channels) basis. By default, the MegaWizard
Plug-In Manager selects a set of clocks for transmitters and receivers in a
transceiver block when XAUI mode is selected. The MegaWizard Plug-In
Manager also offers clock options other than the default selection, which
facilitates the clocking scheme.
Figure 5–21 shows that the altgxb megafunction is configured such that
the train receiver PLL with transmitter PLL is enabled. The transmitter
PLL is fed from an inclk port that can itself be fed from a dedicated
REFCLKB
, global clock, regional clock, or fast regional clock source. The
receiver logic is clocked by the recovered clock from the clock recovery
unit up to a deskew FIFO module in the data path. Rate matching is done
between recovered clock of channel 0 and refclk from the transmitter
PLL. The data from the receive parallel interface, which is also from the
phase compensation FIFO module, is clocked by coreclk_out from the
transmitter PLL. On the transmitter channel, the output of the transmitter
PLL, coreclk_out, is sent out of the logic array as an output and also
loops back to clock the write side of the transmit phase compensation
FIFO module and the read side of the receive phase compensation FIFO
module.