Altera Stratix GX Transceiver - Manual (Page 11)

Altera Corporation 1–3
January 2005 Stratix GX Transceiver User Guide
Introduction
Transmitter & Receiver PLLs
Each gigabit transceiver block contains one dedicated transmitter PLL
and four dedicated receiver PLLs. These PLLs provide clocking flexibility
and support a range of incoming data streams. For data transmission and
recovery, these PLLs generate the required clock frequencies based upon
the synthesis of an input reference clock. Each transmitter PLL supports
multiplication factors of 2, 4, 5, 8, 10, 16, or 20. Either external reference
clocks or a variety of clock sources within the Stratix GX device drive the
PLLs.
Clock Recovery Unit
The gigabit transceiver block clock recovery unit (CRU) performs analog
Clock Data Recovery (CDR). The CRU uses an external reference clock to
extract a recovered clock that is frequency and phase aligned with the
incoming data, thereby eliminating any clock-to-data skew. This
recovered clock then clocks the data through the rest of the gigabit
transceiver block.
Serializer Deserializer (SERDES)
The transmitter serializer converts the incoming lower speed parallel
signal to a high-speed serial signal on the transmit side. The SERDES
supports a variety of conversion factors, ensuring implementation
flexibility. For example, the SERDES supports 10- and 20-bit serialization
factors, typically required for 8B/10B encoded data, as well as 8- and
16-bit factors.
The receiver deserializer converts the incoming data stream from a
high-speed serial signal to a lower-speed parallel signal that can be
processed in the FPGA logic array on the receive side. The SERDES
supports a variety of conversion factors, ensuring implementation
flexibility. For example, the SERDES supports both 10-bit and 8-bit
serialization and deserialization factors.
Digital Overview
This section describes the various components in the digital section of the
transceiver block.