Altera Stratix GX Transceiver - Manual (Page 267)

Altera Corporation 9–41
January 2005 Stratix GX Transceiver User Guide
Reset Control & Power Down
input sync_reset; //Input: synchronous reset from the system
input async_reset; //Input: async reset from system
input receive_digitalreset; //Input : Reset the receiver section
input rx_freqlocked; //rx_freqlocked signal from receive;
Transition from 'lock to reference clock mode' to 'lock to data
mode'
input pll_locked; // Transmit PLL of GXB locked
output rxdigitalreset;//GXB Receive digital reset
output rxanalogreset;//Receive power down signal
output pll_areset;//GXB power down signal
reg rxdigitalreset;
wire rxanalogreset;
reg pll_areset;
reg [2:0] state;
reg rxdigitalreset_inclk;
reg rxanalogreset_inclk;
reg rxdigitalreset_rx_clkout_Q;
reg rxanalogreset_rx_clkout_Q;
parameter IDLE = 3'b000;
parameter STROBE_TXPLL_LOCKED = 3'b001;
parameter STABLE_TX_PLL = 3'b010;
parameter WAIT_STATE = 3'b011;
//Parameter value of T (2ms)based on the fastest clock (or 3.1875
Gbps)
parameter WAITSTATE_TIMER_VALUE = 1000000;
reg [19:0]waitstate_timer; //timer - for actual value, refer
stratix data sheet
assign rxanalogreset = rxanalogreset_inclk;
always @ (posedge inclk or posedge async_reset) begin
if (async_reset)
begin
rxdigitalreset_inclk <= 1'b1;
rxanalogreset_inclk <= 1'b1;
pll_areset <= 1'b1;
waitstate_timer <= WAITSTATE_TIMER_VALUE;
state <= STROBE_TXPLL_LOCKED;
end
else
case (state)
IDLE:
if (sync_reset) //Synchronous Reset can be
asserted in IDLE state (After reset seq has finished)
begin
rxdigitalreset_inclk <= 1'b1;