Altera Stratix GX Transceiver - Manual (Page 3)

Altera Corporation iii
Contents
About This User Guide ............................................................................ vii
How to Contact Altera ........................................................................................................................... vii
Typographic Conventions .................................................................................................................... viii
Chapter 1. Introduction
Gigabit Transceiver Block Highlights ................................................................................................. 1–1
Transceiver Block Architecture ........................................................................................................... 1–2
Analog Section Overview ............................................................................................................... 1–2
Digital Overview .............................................................................................................................. 1–3
Modes of Operation ............................................................................................................................... 1–5
Basic Mode ........................................................................................................................................ 1–5
SONET Mode .................................................................................................................................... 1–6
XAUI Mode ....................................................................................................................................... 1–7
GigE Mode ......................................................................................................................................... 1–8
Loopback ........................................................................................................................................... 1–9
Built-In Self Test ............................................................................................................................... 1–9
Chapter 2. Stratix GX Analog Description
Introduction ............................................................................................................................................ 2–1
Transmitter Analog ............................................................................................................................... 2–2
Transmitter Buffer ............................................................................................................................ 2–2
Transmitter PLL ................................................................................................................................ 2–5
Serializer (Parallel-to-Serial Converter) ........................................................................................ 2–8
Receiver Analog ..................................................................................................................................... 2–9
Receiver Input Buffer ....................................................................................................................... 2–9
Receiver PLL ................................................................................................................................... 2–12
Clock Recovery Unit ...................................................................................................................... 2–16
Deserializer (Serial-to-Parallel Converter) .................................................................................. 2–19
MegaWizard Analog Features ........................................................................................................... 2–20
MegaWizard Analog Feature Considerations ........................................................................... 2–20
Chapter 3. Basic Mode
Introduction ............................................................................................................................................ 3–1
Basic Mode Receiver Architecture ...................................................................................................... 3–2
Word Aligner .................................................................................................................................... 3–2
8B/10B Decoder ................................................................................................................................ 3–9
Byte Deserializer ............................................................................................................................. 3–13
Receiver Phase Compensation FIFO Buffer ............................................................................... 3–15
Basic Mode Transmitter Architecture ............................................................................................... 3–16
Transmitter Phase Compensation FIFO Buffer .......................................................................... 3–16