Altera Stratix GX Transceiver - Manual (Page 233)

Altera Corporation 9–7
January 2005 Stratix GX Transceiver User Guide
Reset Control & Power Down
Design Example 1
This design example shows inclk as the input reference clock and the
transmit parallel clock and rx_coreclk as the receive parallel clock. The
design example has the following constraints:
■ If your design requirements are different from the examples, use the
flow charts and waveforms for each configuration as design
guidelines.
■ The design example requires a reset controller that generates a
sync_reset
(synchronous reset) for the entire system.
■ The design example has an async_reset (a power down in GXB
terms) and digital resets for transmit and receive. All user input
digital resets must be at least four cycles long.
■ This design example does not cover all the digital reset scenarios in
a system that resets the digital logic of the GXB.
■ In this example, whenever the rx_freqlocked signal toggles the
rxdigitalreset
, the receiver’s digital circuit is reset. However,
you can make changes to the design to avoid this if, for example, you
want to debug your design without the core being reset.
■ If you plan to use REFCLKB pins in your design, see Appendix C,
REFCLKB Pin Constraints for information about the effects of analog
resets (pll_arest, rx_analogreset).
/*
Copyright (c) Altera Corporation, 2004.
This file may contain proprietary and confidential information
of Altera Corporation
=================
We have made every effort to ensure that this design example works
correctly. If you have a question or problem that is not answered
by the information then please contact Altera Support.
****************************************************************
Reset Sequence for the ALTGXB. The configuration of GXB for which
the following reset sequence is valid is:
Transmit and Receive : Both used
Datapath : Single Width(8/10 bits)
receive parallel clock: rx_coreclk
Functional Mode :'Any'
RX PLL CRU : Train RX PLL CRU with TX PLL ouput clock
***************************************************************/
`timescale 1ns/10ps
module reset_seq_tx_train_rx_rx_coreclk (
rx_coreclk,
inclk,
sync_reset,
async_reset,
transmit_digitalreset,