Altera Stratix GX Transceiver - Manual (Page 281)

Altera Corporation 9–55
January 2005 Stratix GX Transceiver User Guide
Reset Control & Power Down
■ If you plan to use REFCLKB pins in your design, see Appendix C,
REFCLKB Pin Constraints for information about the effects of analog
resets (pll_arest, rx_analogreset).
/*
Copyright (c) Altera Corporation, 2004.
This file may contain proprietary and confidential information of
Altera Corporation
Contacting Altera
=================
We have made every effort to ensure that this design example works
correctly. If you have a question that is not answered by the
information, please contact Altera Support.
****************************************************************
Reset Sequence for the ALTGXB. The configuration of GXB for which
the following
reset sequence is valid is:
Transmit and Receive : Transmit ONLY
Datapath : Single Width(8/10 bits) or Double Width (16/20
bits)
Transmit parallel clock: '-'
Functional Mode :'Any'
***************************************************************/
`timescale 1ns/10ps
module reset_seq_tx_ONLY (
inclk,
sync_reset,
async_reset,
transmit_digitalreset,
pll_locked,
pll_areset,
txdigitalreset
);
input inclk; //GXB input reference clock
input sync_reset; //Input: synchronous reset from the system
input async_reset; //Input: async reset from system
input transmit_digitalreset; //Input: Reset only the transmit
digital section
input pll_locked; // Transmit PLL of GXB locked