Altera Stratix GX Transceiver - Manual (Page 90)

4–8 Altera Corporation
Stratix GX Transceiver User Guide January 2005
SONET Mode Receiver Architecture
Byte Deserializer
The byte deserializer module further reduces the speed that the FPGA
logic array must achieve in order to meet performance. The possible
division factors are 8 and 16. This requirement results in a byte or double
byte data width in the PLD logic array.
In SONET mode, the maximum output bus width is 22 bits. If the input
includes data and control signals, the data and the control signals are
deserialized to include double the data bits and 2 bits of each control
signal, one for the MSB and one for the LSB. This case is shown when in
SONET mode where the inputs to the Byte Deserializer are
datain[7..0]
, rx_syncstatus, rx_patterndetect, and
rx_a1a2sizeout . These total 11 input signals feeding the byte
deserializer and 22 output signals are fed to the FPGA logic array. The
signals are sent into the logic array as two 11-bit buses. The aggregate
bandwidth does not change by use of the Byte Deserializer because the
logic array data width is doubled.
Figure 4–6 demonstrates input and output signals of the byte deserializer
when deserializing an 8-bit data input to 16-bits. In this case, the finishing
alignment pattern A2 (00010100) shown as 'B' is located in the MSB of the
16-bit output and this is reflected with patterndetect [1] going high.
The output of the byte deserializer is BA, DC, FE, and so on. This example
assumes that the word alignment bit-flip option is unchecked (OFF), and
that the transmitter and receiver bit-flip option is checked (ON) to adhere
to the MSB transmitted first option.
Figure 4–6. Receiver Byte Deserializer in 8/16-Bit Mode With Finishing Alignment Pattern in MSB
inclk
data_in[7..0]
data_out[15..0]
patterndetect[0]
patterndetect[1]
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00010100 11000110 01101111
A B C
11110001
D
11001100
F
10101010
E
0001010001101111
BA
1111000111000110
DC