Altera Stratix GX Transceiver - Manual (Page 241)

Altera Corporation 9–15
January 2005 Stratix GX Transceiver User Guide
Reset Control & Power Down
begin
rxdigitalreset_inclk <= 1'b1;
rxanalogreset_inclk <= 1'b1;
txdigitalreset <= 1'b1;
pll_areset <= 1'b1;
state <= STROBE_TXPLL_LOCKED;
end
//Wait untill the TXPLL is locked to inclk and TX PLL has a
stable output clock which is also fed to RX CRU
else if (pll_locked)
begin
state <= STABLE_TX_PLL;
rxdigitalreset_inclk<= 1'b1;
rxanalogreset_inclk <= 1'b0;
txdigitalreset<= 1'b0;
pll_areset <= 1'b0;
end
else
begin
state <= STROBE_TXPLL_LOCKED;
rxdigitalreset_inclk <= 1'b1;
rxanalogreset_inclk <= 1'b1;
txdigitalreset <= 1'b1;
pll_areset <= 1'b0;
end
STABLE_TX_PLL: if (sync_reset) //Synchronous Reset can
be asserted in IDLE state (After reset seq has finished)
begin
rxdigitalreset_inclk <= 1'b1;
rxanalogreset_inclk <= 1'b1;
txdigitalreset <= 1'b1;
pll_areset <= 1'b1;
state <= STROBE_TXPLL_LOCKED;
end
else if (rx_freqlocked)
begin
state <= WAIT_STATE;
waitstate_timer <= waitstate_timer -
1'b1 ;
rxdigitalreset_inclk<= 1'b1;
rxanalogreset_inclk <= 1'b0;
txdigitalreset<= 1'b0;
pll_areset <= 1'b0;
end
else
begin
state <= STABLE_TX_PLL;
rxdigitalreset_inclk<= 1'b1;
rxanalogreset_inclk <= 1'b0;
txdigitalreset<= 1'b0;
pll_areset <= 1'b0;
end
WAIT_STATE: if (sync_reset) //Synchronous Reset can be
asserted in IDLE state (After reset seq has finished)
begin
rxdigitalreset_inclk <= 1'b1;
rxanalogreset_inclk <= 1'b1;
txdigitalreset <= 1'b1;