Altera Stratix GX Transceiver - Manual (Page 9)

Altera Corporation 1–1
January 2005
1. Introduction
Introduction Stratix ® GX devices combine highly advanced 3.1875-gigabit-per-second
(Gbps) four-channel gigabit transceiver blocks with one of the industry’s
most advanced FPGA architectures. Stratix GX devices are manufactured
on a 1.5-V, 0.13-µm, all-layer copper CMOS process technology with 1.5-
V PCML I/O standard support.
Historically, designers have used high-speed transceivers in strictly
structured, line-side applications. Now, with the new gigabit transceiver
blocks embedded in FPGAs, you can use transceivers in a host of new
systems that require flexibility, increased time-to-market, high
performance, and top-of-the-line features.
Gigabit
Transceiver
Block Highlights Stratix GX devices are organized into four-channel blocks with four
3.1875 Gbps full-duplex channels per block and up to 20 channels (in five
blocks) per device. Each self-contained Stratix GX gigabit transceiver
block supports a variety of embedded functions and does the following:
■ Supports frequencies from 500 megabits per second (Mbps) to
3.1875 Gbps
■ Integrates serializer/deserializer (SERDES), clock data recovery
(CDR), word aligner, channel aligner, rate matcher, 8B/10B
encoder/decoder, byte serializer/deserializer, and phase
compensation first-in first-out (FIFO) modules
■ Supports flexible reference clock generation capabilities, including a
dedicated transmitter phase-locked loop (PLL) and four receiver
PLLs per gigabit transceiver block
■ Supports programmable pre-emphasis, equalization, and
programmable V
OD
settings in I/O buffers, and dynamic
reprogrammability for each of these features
■ Implements XAUI physical media attachment (PMA) and physical
coding sublayer (PCS) functionality for 10GBASE-X systems
■ Provides built-in Gigabit Ethernet (GigE) physical coding sublayer
functionality
■ Provides individual transmitter and receiver power-down capability
for reduced power consumption during non-operation
■ Includes built-in self test (BIST) capability, including embedded
Pseudo Random Binary Sequence (PRBS) pattern generation and
verification
■ Includes three independent loopback paths for system verification