Altera Stratix GX Transceiver - Manual (Page 301)

Altera Corporation B–5
January 2005 Stratix GX Transceiver User Guide
Output Ports Table B–2 lists the output ports of the Stratix GX device.
Table B–2. Output Ports (Part 1 of 4)
Port Name Required Description Comments
pll_locked[] No Gives the status of the
transceiver block
transmitter PLL. Output port [NUMBER_OF_QUADS - 1..0]
wide. The
pll_locked port is available
only when the transceiver block transmitter
PLL is used. The signal achieves lock
status within several clock cycles in
simulation. This does not necessarily reflect
the real lock time in the hardware, which
can take thousands of cycles for some
settings.
coreclk_out[] No Output clock fed by the
clk2 port of the
transceiver block
transmitter PLL. Output port [NUMBER_OF_QUADS - 1..0]
wide. If a transceiver block transmitter PLL
is used, the
coreclk_out port must be
enabled.
rx_out[] Yes Transceiver block
receiver PLL output
data. Output port [CHANNEL_WIDTH *
NUMBER_OF_CHANNELS - 1..0] wide. If
you set the
USE_8B_10B_MODE
parameter to OFF and the
USE_DOUBLE_DATA_MODE parameter is
set to OFF , the deserialization factor is
CHANNEL_WIDTH . If you set the
USE_8B_10B_MODE parameter to OFF
and the USE_DOUBLE_DATA_MODE
parameter is set to ON , the deserialization
factor is CHANNEL_WIDTH / 2. If you set
the USE_8B_10B_MODE parameter to ON ,
the deserialization factor is 10.