Altera Stratix GX Transceiver - Manual (Page 93)

Altera Corporation 4–11
January 2005 Stratix GX Transceiver User Guide
SONET Mode
for the read clock. Refer to “SONET Mode Channel Clocking” on
page 4–12 or the block diagram in the MegaWizard Plug-In Manager for
more information on the clock structure in a particular mode.
The Receiver Phase Compensation FIFO module is always used and
cannot be bypassed.
SONET Mode
Transmitter
Architecture Figure 4–9 shows a diagram of the digital components of the transmitter.
The rest of this section describes the active components of the transmitter,
which are the phase compensation FIFO buffer and the byte serializer.
The 8B/10B decoder is not active during SONET mode.
Figure 4–9. Block Diagram of the Transmitter Digital Components in SONET Mode
Transmitter Phase Compensation FIFO Buffer
The transmitter phase compensation FIFO buffer is located at the FPGA
logic array interface in the transmitter block and is four words deep. The
phase compensation FIFO module compensates for the phase difference
between the clock in the FPGA and the operating clocks in the transceiver
block.
The read port of the phase compensation FIFO buffer is clocked by the
transmitter PLL clock. The write clock is clocked by tx_coreclk. You
can select the tx_coreclk as an optional transmitter input port to
supply a clock to. In this case, you must ensure that there is no frequency
difference between the tx_coreclk and the transmitter PLL clock. The
transmitter phase compensation FIFO module can only account for phase
differences.
If the tx_coreclk is not selected as an optional input transmitter port,
tx_coreclk
is fed by coreclk_out. This connection occurs using the
logic array routing. In this case, the software defaults to using an FPGA
global clock, regional clock, or fast regional clock resource.
Serializer
Reference
Clock
Byte
Serializer
Transmitter
Phase
Compensation
FIFO Buffer
Transmitter
PLL
8B/10B
Encoder
Digital Section Analog Section