Altera Stratix GX Transceiver - Manual (Page 66)

3–20 Altera Corporation
Stratix GX Transceiver User Guide January 2005
Basic Mode Clocking
An example would be the invalid code encoding of a K24.1 (data =
8'h38 + tx_ctrlenable = 1'b1
). Depending on the current running
disparity, the K24.1 can be encoded to be 10'b0110001100 (0x18C), which
is equivalent to a D24.6+ (0xD8 from the RD+ column). An 8B/10B
decoder would decode this value incorrectly.
Basic Mode
Clocking Two types of clocking are available in basic mode: channel clocking and
inter-transceiver clocking.
Basic Mode Channel Clocking
This section describes internal clocking and the external clocks of the
transceiver in basic mode. By default, the MegaWizard Plug-In Manager
parameterizes the altgxb megafunction with the clock configuration
shown in
Figure 3–19 .
Figure 3–19. Default Configuration of the altgxb Megafunction in Basic Mode
The altgxb megafunction (shown in basic mode in Figure 3–19 ) is
configured such that the train receiver PLL with transmitter PLL is
enabled. The transmitter PLL is fed from an inclk port, which itself can
be fed from a dedicated REFCLKB, global clock, regional clock, or fast
regional clock source. The receiver logic is clocked by the recovered clock
from the CRU, which is rx_clkout. This recovered clock is also fed into
the device so that in a multi-crystal environment, some level of clock
domain decoupling can be implemented to interface with a system clock.