Altera Stratix GX Transceiver - Manual (Page 69)

Altera Corporation 3–23
January 2005 Stratix GX Transceiver User Guide
Basic Mode
Figure 3–21. altgxb in Basic Mode With rx_coreclk & tx_coreclk Enabled
Table 3–3 displays a list of the input and output clock ports available in
basic mode.
Table 3–3. Input & Output Ports Available in Basic Mode (Part 1 of 2)
Clock Port Description
rx_cruclk Input Input to CRU available as a port when CRU is not
trained by the transmitter PLL.
inclk Input Input to transmitter PLL available as a port when the
transmitter PLL is instantiated.
coreclk_out Output Output clock from transmitter PLL equivalent to
TX_PLL_CLK . Available as port if transmitter PLL is
used.
rx_clkout Output Output clock from transceiver. In this mode,
RX_CLKOUT is the recovered clock of the respective
channel.