Altera Stratix GX Transceiver - Manual (Page 270)

9–44 Altera Corporation
Stratix GX Transceiver User Guide January 2005
Recommended Resets
pll_areset <= 1'b0;
waitstate_timer <=
WAITSTATE_TIMER_VALUE;
state <= STABLE_TX_PLL;
end
default: state = IDLE;
endcase
end
/*synchronizing the rxdigitalreset to recovered clock domain
If rxdigitalreset is only used for receive GXB, synchronization
is redundant because internally the rxdigitalreset is
synchronized to the recovered clock (rx_clkout). In the above
description of the module, User likes to operate on the system
clock or PLD clock domain where one would like to have a FIFO with
rx_clkout domain being write clock and pld clock domain (generic
name, can be any clock name) as read clock.
To reset the rx_clkout domain logic in PLD fabric following reset
is useful
*/
always @(posedge rx_clkout or posedge async_reset)
if(async_reset)
begin
rxdigitalreset_rx_clkout_Q <= 1'b1;
rxdigitalreset <= 1'b1;
end
else
begin
if(receive_digitalreset)
begin
rxdigitalreset_rx_clkout_Q <= 1'b1;
rxdigitalreset <= 1'b1;
end
else
begin
rxdigitalreset_rx_clkout_Q <=
rxdigitalreset_inclk;
rxdigitalreset <=
rxdigitalreset_rx_clkout_Q;
end
end
endmodule
Receive CRU With Transmit PLL Output Clock Option Disabled
This section provides examples that show a receive-only configuration
with a train receive CRU and the transmitter PLL output clock option
disabled. The flow chart in
Figure 9–11 on page 9–33 and the waveform
shown in Figure 9–12 on page 9–34 are valid for this configuration also.