Altera Stratix GX Transceiver - Manual (Page 35)

Altera Corporation 2–17
January 2005 Stratix GX Transceiver User Guide
Stratix GX Analog Description
During the lock-to-reference mode, the frequency detector determines
whether the reference clock to the receiver PLL and the VCO output are
within the prescribed PPM setting.
The phase lock happens when the phase-frequency detector up/down
transitions are relatively few and, the pulse widths are sufficiently
narrow. These conditions show that the PLL is close to absolute phase
lock to the reference clock. This ensures that when actual data signals are
sampled, the receiver PLL locks to the fundamental REFCLK frequency
and does not drift off to any sub-harmonic.
In lock-to-data mode, the PLL uses a phase detector to keep the recovered
clock aligned properly with the data. If the PLL does not stay locked to
data because of problems such as frequency drift or severe amplitude
attenuation, the receiver PLL locks back to the reference clock of the CRU
to train the VCO. When the device is in lock-to-data mode, the CRU tries
to align itself with incoming data and there is no phase relationship with
the reference clock.
In lock-to-data mode, the rx_freqlocked signal is asserted, and the
rx_locked
signal looses its significance. The rx_locked signal
signifies that the CRU has locked to the reference clock. When the CRU is
in lock-to-data mode, the rx_locked signal behavior is not predictable.
In automatic lock mode, CRU is forced out of lock-to-data mode if the
CRU PLL is not within the recommended PPM frequency threshold
setting (125 PPM, 250 PPM, 500 PPM, 1000 PPM) of the CRU reference
clock.
When the CRU goes out of lock-to-data mode, the rx_freqlocked
signal goes low. The rx_freqlocked signal also goes low when either
the rx_analogreset or pll_areset signal goes high. The
rx_analogreset
signal powers down the receiver and the
pll_areset signal powers down the entire transceiver block (four
channels).
Manual Lock Options
Two optional input pins, rx_locktorefclk[] and
rx_locktodata[]
, are available that let you control whether the CRU
PLL automatically or manually switches between lock-to-reference clock
and lock-to-data modes. This lets you bypass the default automatic
switchover circuitry if either the rx_locktorefclk[] or
rx_locktodata[]
signal is instantiated.
When the rx_locktorefclk[] signal is asserted, it forces the CRU PLL
to lock to the reference clock (RX_CRUCLK). Asserting the
rx_locktodata[]
signal forces the CRU PLL to lock to data, whether