Altera Stratix GX Transceiver - Manual (Page 272)

9–46 Altera Corporation
Stratix GX Transceiver User Guide January 2005
Recommended Resets
■ If you plan to use REFCLKB pins in your design, see Appendix C,
REFCLKB Pin Constraints for information about the effects of analog
resets (pll_arest, rx_analogreset).
/*
Copyright (c) Altera Corporation, 2004.
This file may contain proprietary and confidential information of
Altera Corporation
Contacting Altera
=================
We have made every effort to ensure that this design example works
correctly. If you have a question that is not answered by the
information, please contact Altera Support.
****************************************************************
Reset Sequence for the ALTGXB. The configuration of GXB for which
the following
reset sequence is valid is:
Transmit and Receive : Receive Only
Datapath : Single Width(8/10 bits)
receive parallel clock: rx_coreclk
Functional Mode :'Any'
RX PLL CRU : rx_cruclk
***************************************************************/
`timescale 1ns/10ps
module reset_seq_rx_rx_cruclk_rx_coreclk (
rx_coreclk,
rx_cruclk,
sync_reset,
async_reset,
receive_digitalreset,
rx_freqlocked,
rxanalogreset,
rxdigitalreset
);
input rx_cruclk; //Receive GXB input reference clock
input rx_coreclk;//Receive recovered clock
input sync_reset; //Input: synchronous reset from the system
input async_reset; //Input: async reset from system
input receive_digitalreset; //Input : Reset the receiver section
input rx_freqlocked; //rx_freqlocked signal from receive;
Transition from 'lock to reference clock mode' to 'lock to data
mode'