Altera Stratix GX Transceiver - Manual (Page 209)

Altera Corporation 8–5
January 2005 Stratix GX Transceiver User Guide
Stratix GX Built-In Self Test (BIST)
Low-frequency mode is enabled when you select the SELF_ option 3 in
the Quartus II software under what self test mode do you want to use?
You must enable the 8b/10b encoder to generate the high-frequency
pattern. If it is disabled, an 8'b11111100 character is sent instead of the
10'b0011111000
or 10'b1100000111 characters.
Mix-Frequency Mode Generator
In mix-frequency mode, the BIST generator transmits a K28.5 -/+
character (8'b10111100) character into the 8b/10b encoder to generate
a 10'b0011111010 or 10'b1100000101 mixed-frequency character.
The mixed frequency pattern contains both high-frequency and
low-frequency components. This approach is useful for first-order
approximation of the frequency response of the transmission medium. If
captured with an oscilloscope, these frequency responses are
approximated in time domain.
Mix-frequency mode is enabled when you select option 4 in the
Quartus II software under what self test mode do you want to use? As in
the high-frequency and low-frequency modes, you must enable the
8b/10b encoder in order to generate the mixed-frequency pattern.
Pattern Verifier The BIST verifier supports the PRBS and incremental modes.
PRBS Mode Verifier
The PRBS verifier provides a quick check through the non-8b/10b path of
the transceiver block. You must select the internal or external loopback
mode to loop the generated data back into the verifier in the receiver.
Select either a serial or parallel loopback to provide this path. A parallel
loopback tests the digital portion of the transceiver while a serial
loopback also tests the analog clock recovery unit (CRU) and the
serializer and deserializer.
The PRBS verifier is active when the receiver channel is synchronized.
The alignment pattern must be set to 16'b1000000011111111 for the
8- and 16-bit modes and to 10'b111111111 for the 10- and 20-bit modes.
The data is synchronized automatically with a built in state machine, so
the rx_enacdet signal is not required.
The verifier stops checking the patterns after receiving all the PRBS
patterns (255 patterns for 8-bit mode and 1023 patterns for 10-bit mode).
The rx_bistdone signal goes high, indicating that the verifier has
completed. If the verifier detects an error before it is finished,
rx_bisterr
goes high and the value will be latched until it is reset. The
rxdigitalreset signal must be used to re-start the PRBS verification.