Altera Stratix GX Transceiver User Manual

Page 275

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Altera Corporation

9–49

January 2005

Stratix GX Transceiver User Guide

Reset Control & Power Down

Design Example 2
This design example shows a receive-only configuration with
rx_cruclk

as the receive CRU input reference clock and rx_clkout as

the receive parallel interface clock.

This design example has the following constraints:

If your design requirements are different from the examples, use the
flow charts and waveforms for each configuration as design
guidelines.

The design example requires a reset controller that generates a
sync_reset

(synchronous reset) for the entire system.

The design example has an async_reset (a power down in GXB
terms) and digital resets for transmit and receive. All user input
digital resets must be at least four cycles long.

This design example does not cover all the digital reset scenarios in
a system that resets the digital logic of the GXB.

In this example, whenever the rx_freqlocked signal toggles the
rxdigitalreset

, the receiver’s digital circuit is reset. However,

you can make changes to the design to avoid this if, for example, you
want to debug your design without the core being reset.

If you plan to use REFCLKB pins in your design, see

Appendix C,

REFCLKB Pin Constraints

for information about the effects of analog

resets (pll_arest, rx_analogreset).

/*

Copyright (c) Altera Corporation, 2004.

This file may contain proprietary and confidential information of

Altera Corporation

Contacting Altera

=================

we have made every effort to ensure that this design example works

correctly. If you have a question that is not answered by the

information, please contact Altera Support.

****************************************************************

Reset Sequence for the ALTGXB. The configuration of GXB for which

the following

reset sequence is valid is:

Transmit and Receive : Receive Only

Datapath

: Single Width(8/10 bits) or Double Width(16/20

bits)

receive parallel clock: rx_clkout

Functional Mode :'Any'

RX PLL CRU : rx_cruclk

***************************************************************/

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