Altera Stratix GX Transceiver - Manual (Page 30)

2–12 Altera Corporation
Stratix GX Transceiver User Guide January 2005
Receiver Analog
This variation in frequency response yields data-dependant jitter and
other ISI effects. By applying equalization, the low frequency components
are attenuated. This equalizes the frequency response so that the delta
between the low frequency and high frequency components are reduced,
which minimizes the ISI effects from the transmission medium.
In Stratix GX transceivers, the programmable equalizer settings can have
one of five values (0 through four). You should experiment with the
equalization values to determine the optimal setting based on your
system variables.
As with the V
OD
settings, you can set the equalization settings statically
during configuration or adjust them dynamically in user mode. You can
select the static equalization value through a drop-down menu in the
altgxb
MegaWizard Plug-In. This action sets the appropriate
equalization setting in the configuration file. The disadvantage of this
mode is that the equalization is set on a per-transceiver block basis and
cannot be changed without regenerating another programming file.
On the other hand, if you select the dynamic adjustment in the altgxb
MegaWizard Plug-In, the equalization setting can be configured
dynamically by the device during user mode. This configuration is
accomplished by asserting encoded values on the rx_equalizerctrl
signal, which is instantiated in the altgxb module when this option is
selected. This feature lets you make quick performance evaluations of the
various settings without having to recompile and regenerate multiple
configuration files. Another advantage is that this option allows the
equalization of each channel to be configured independently. Refer to
“MegaWizard Analog Features” on page 2–20 for more details.
Receiver PLL
Each transceiver block contains four receiver PLLs and a slow-speed
reference clock. The receiver PLLs receive the reference clock and
generate the high-speed serial clock used by the CR. The slow-speed
reference clock is used for the transceiver logic.
Figure 2–10 shows the
block diagram for the lock-to-reference portion of the receiver PLL.
This section focuses on the receiver PLL in Lock-to-Reference mode. The
lock-to-data circuit has been omitted. Refer to the
“Lock-to-Reference
Mode & Lock-to-Data Mode” on page 2–16 for more information on the
operation between the two modes.