Altera Stratix GX Transceiver - Manual (Page 151)

Altera Corporation 5–39
January 2005 Stratix GX Transceiver User Guide
XAUI Mode
Figure 5–32. MegaWizard Plug-In Manager - ALTGXB (Page 7 of 9) - Receiver (3) Notes (1) – (5)
Notes to Figure 5–32 :
(1) For more information, refer to the Stratix GX Analog Description chapter.
(2) Receiver PLL lock indicator. For rx_locked, Low = receiver PLL locked to reference clock.
(3) rx_signaldetect is only available in XAUI mode. Because the signal detect circuitry is always forced, the
rx_signaldetect signal is always set in XAUI and GIGE modes, supporting backward compatibility with
existing designs. See the Stratix GX Analog Description chapter for additional information.
(4) Indicates when the word aligner has aligned to the byte boundary. The rx_syncstatus signal goes high for
one rx_clkout period when the word aligner aligns to the new byte boundary. If in 16-bit mode, each high and
low byte has a separate rx_syncstatus signal.
(5) rx_patterndetect is similar to the rx_syncstatus , except that rx_patterndetect asserts only
when the word alignment pattern appears in the data stream within the synchronized byte boundary.