Altera Stratix GX Transceiver - Manual (Page 182)

6–28 Altera Corporation
Stratix GX Transceiver User Guide January 2005
GigE Mode Clocking
Figure 6–25. Inter-transceiver Line Connections for EP1SGX25F Device
16
IQ0 IQ1 IQ2
Transceiver Block 0
IQ0
IQ1
Global Clocks, I/O Bus, General Routin g
Global Clocks, I/O Bus, General Routin g
Transmitter
PLL
IQ2
/2
4 4
Receiver
PLLs
PLD Global Clocks
Transceiver Block 1
IQ0
IQ1
Global Clocks, I/O Bus, General Routin g
Global Clocks, I/O Bus, General Routin g
Transmitter
PLL
IQ2
/2
4 4
Receiver
PLLs
Transceiver Block 2
IQ0
IQ1
Global Clocks, I/O Bus, General Routin g
Global Clocks, I/O Bus, General Routin g
Transmitter
PLL
IQ2
/2
4 4
Receiver
PLLs
Transceiver Block 3
IQ0
IQ1
Global Clocks, I/O Bus, General Routin g
Global Clocks, I/O Bus, General Routin g
Transmitter
PLL
IQ2
/2
4 4
Receiver
PLLs
refclkb
refclkb
refclkb
refclkb