Altera Stratix GX Transceiver User Manual
Page 298
B–2
Altera Corporation
Stratix GX Transceiver User Guide
January 2005
Input Ports
rx_enacdet[]
No
Enables alignment
to the programmed
pattern.
Input port [NUMBER_OF_CHANNELS -
1..0] wide. If you enable the
rx_enacdet
port, the
rx_bitslip[]
port cannot be
connected, and the
USE_AUTO_BIT_SLIP
parameter must
be set to
ON
.
rx_slpbk[]
No
Serial loopback
input. Dynamically
enables serial
loopback from the
transceiver block
transmitter to the
transceiver block
receiver in the same
channel.
Input port [NUMBER_OF_CHANNELS -
1..0] wide. If you enable the
rx_slpbk[]
input port, the
OPERATION_MODE
parameter must be set to
DUPLEX
, and the
serialfdbk
port of the transceiver block
receiver channel must be connected.
rx_a1a2size[]
No
Detects A1A2 or
A1A1A2A2 input
patterns. If the
signal is low (0),
A1A2 patterns are
detected. If the
signal is high (1),
A1A1A2A2 patterns
are detected.
Input port [NUMBER_OF_CHANNELS -
1..0] wide. If you enable the
rx_a1a2size[]
port, the
PROTOCOL
parameter must be set to
SONET
.
rx_equalizerctrl[]
No
Specifies the
equalizer control
setting.
Input port [NUMBER_OF_CHANNELS *
3..0] wide. Use the following settings:
rx_locktorefclk[]
No
Control signal for
transceiver block
receiver PLL to lock
to the reference
clock.
Input port [NUMBER_OF_CHANNELS -
1..0] wide.
Table B–1. Input Ports (Part 2 of 4)
Port Name
Required
Description
Comments
Incoming Signal
000
001
010
011
100
101
110
111
Equalizer
Control Setting
0
Reserved
1
Reserved
2
3
Reserved
4