Altera Stratix GX Transceiver - Manual (Page 282)

9–56 Altera Corporation
Stratix GX Transceiver User Guide January 2005
Recommended Resets
output txdigitalreset; //GXB transmit digital reset
output pll_areset;//GXB power down signal
reg txdigitalreset;
reg pll_areset;
reg [1:0] state;
parameter IDLE = 2'b00;
parameter STROBE_TXPLL_LOCKED = 2'b01;
always @ (posedge inclk or posedge async_reset) begin
if (async_reset)
begin
txdigitalreset <= 1'b1;
pll_areset <= 1'b1;
state <= STROBE_TXPLL_LOCKED;
end
else
case (state)
IDLE:
if (sync_reset) //Synchronous Reset can be
asserted in IDLE state (After reset seq has finished)
begin
txdigitalreset <= 1'b1;
pll_areset <= 1'b1;
state <= STROBE_TXPLL_LOCKED;
end
else
begin
pll_areset <= 1'b0;
state <= IDLE;
if(transmit_digitalreset)
txdigitalreset <= 1'b1;
else
txdigitalreset <= 1'b0;
end
STROBE_TXPLL_LOCKED: if (sync_reset) //Synchronous Reset
can be asserted in IDLE state (After reset seq has finished)
begin
txdigitalreset <= 1'b1;
pll_areset <= 1'b1;
state <= STROBE_TXPLL_LOCKED;
end
//Wait untill the TXPLL is locked to inclk and TX PLL has a
stable output clock which is also fed to RX CRU