Altera Stratix GX Transceiver - Manual (Page 178)

6–24 Altera Corporation
Stratix GX Transceiver User Guide January 2005
GigE Mode Clocking
Figure 6–23. TX_CORECLK & RX_CORECLK Enabled With RX_CRUCLK Port Note (1)
Note to Figure 6–23 :
(1) The RX_CORECLK port is enabled for the rate-matching FIFO buffer.
Table 6–2 summarizes the clocks that are used in GigE mode.
Table 6–2. Clocks in GigE Mode (Part 1 of 2)
Clock Port Description
INCLK Input Input to transmitter PLL. Available as a port when transmitter PLL is instantiated.
RX_CRUCLK Input Input to CRU. Available as a port when CRU is not trained by transmitter PLL.