Altera Stratix GX Transceiver - Manual (Page 96)

4–14 Altera Corporation
Stratix GX Transceiver User Guide January 2005
SONET Mode Clocking
frequency detector of the receiver PLL. For more information on this
feature, refer to the Stratix GX Analog Description chapter. This
configuration is shown in
Figure 4–12 .
If double width is used (16-bit bus) and the data rate is above 2,600 Mbps,
the trained receiver PLL clock from the transmitter PLL must be turned
off, because the output clock from the transmitter PLL exceeds the 325-
MHz limit on the receiver PLL input clock, if the input clock is fed from
any non-REFCLKB pin. REFCLKB pins have a 650-MHz limit.
Figure 4–12. altgxb Megafunction in SONET Mode With Train Receiver CRU From Transmitter PLL Disabled
This configuration contains an independent rx_cruclk, which feeds the
receiver PLL reference clock. This input clock port is only available when
the receiver PLL is not trained by the transmitter PLL. One rx_cruclk
is
associated with a channel. If four channels are active, there are four
rx_cruclks .
The rx_clkout is the recovered clock from the associated receiver
channel. An rx_clkout is available for each receiver channel that is
used. This clock is used to clock the write port of a rate matching FIFO
module. The read port of the FIFO module is clocked by the
coreclk_out
or PLD clock.