Altera Stratix GX Transceiver - Manual (Page 238)

9–12 Altera Corporation
Stratix GX Transceiver User Guide January 2005
Recommended Resets
else
begin
rxdigitalreset_rx_coreclk_Q <=
rxdigitalreset_inclk;
rxdigitalreset <=
rxdigitalreset_rx_coreclk_Q;
end
end
endmodule
Design Example 2
The following design example shows inclk as the input reference clock
and the transmit parallel clock and rx_clkout as the receive parallel
clock.
This design example has the following constraints:
■ If your design requirements are different from the examples, use the
flow charts and waveforms for each configuration as design
guidelines.
■ The design example requires a reset controller that generates a
sync_reset
(synchronous reset) for the entire system.
■ The design example contains an async_reset (a power down in
GXB terms) and digital resets for transmit and receive. All user input
digital resets must be at least four cycles long.
■ This design example does not cover all the digital reset scenarios in
a system that resets the digital logic of the GXB.
■ In this example, whenever the rx_freqlocked signal toggles the
rxdigitalreset
, the receiver’s digital circuit is reset. However,
you can make changes to the design to avoid this if, for example, you
want to debug your design without the core being reset.
■ If you plan to use REFCLKB pins in your design, see Appendix C,
REFCLKB Pin Constraints for information about the effects of analog
resets (pll_arest, rx_analogreset).
/*
Copyright (c) Altera Corporation, 2004.
This file may contain proprietary and confidential information of
Altera Corporation
Contacting Altera
=================
We have made every effort to ensure that this design example works
correctly. If you have a question or problem that is not answered
by the information then please contact Altera Support.
****************************************************************
Reset Sequence for the ALTGXB. The configuration of GXB for which
the following
reset sequence is valid is: