Altera Stratix GX Transceiver - Manual (Page 242)

9–16 Altera Corporation
Stratix GX Transceiver User Guide January 2005
Recommended Resets
pll_areset <= 1'b1;
state <= STROBE_TXPLL_LOCKED;
end
else if(rx_freqlocked) //Condition to have
rx_freqlocked signal a stable high and should not bounce around
begin
//Decrement a Timer of 2ms (Refer
Stratix GX Datasheet for accurate value)after rx_freqlocked is
asserted
//This time is given to ensure the
recovered clock to be stable (No freq variations) and is locked
to incomming data
if(waitstate_timer == 0)
begin
state <= IDLE;
rxdigitalreset_inclk<= 1'b0;
rxanalogreset_inclk <=
1'b0;
txdigitalreset<= 1'b0;
pll_areset <= 1'b0;
end
else
begin
waitstate_timer <=
waitstate_timer - 1'b1;
rxdigitalreset_inclk<= 1'b1;
rxanalogreset_inclk <=
1'b0;
txdigitalreset<= 1'b0;
pll_areset <= 1'b0;
state<= WAIT_STATE;
end
end
else
begin
rxdigitalreset_inclk<= 1'b1;
rxanalogreset_inclk <= 1'b0;
txdigitalreset<= 1'b0;
pll_areset <= 1'b0;
waitstate_timer <=
WAITSTATE_TIMER_VALUE;
state <= STABLE_TX_PLL;
end
default: state = IDLE;
endcase
end
/*synchronizing the rxdigitalreset to recovered clock domain
If rxdigitalreset is only used for Receive GXB, then this
synchronization is redundant because
internally the rxdigitalreset is synchronized to recovered clock
(rx_clkout). In the above description
of the module, a typical designer likes to operate on the system
clock
or PLD clock domain where one would like to have a FIFO with
rx_clkout domain being write clock and